Open Access Research Article

Optimized Design of the 100-V Silicon Based Power N-Channel LDMOS Transistor

Shen Li Chen* and SP Lee

Department of Electronic Engineering, National United University, Taiwan

Corresponding Author

Received Date: July 02, 2020;  Published Date: July 21, 2020


In power integrated circuits (PICs), it is desirable to minimize the area of a power device region while maximizing its performances (i.e., higher breakdown voltage and lower on-resistance). Therefore, the area of a power device region mainly determines the total chip size and hence the cost. An optimized design of breakdown voltage and on-resistance in a power n-channel lateral-diffused MOSFET (nLDMOS) was investigated in this paper. Two-dimensional process and device simulators, such as the TSUPREM4 and Sentaurus EDA tools, will be used to predict the device characteristic behaviors. Eventually, it can be shown that a 100 V device will have an optimized breakdown voltage about 156.7 volts and onresistance Ron about 40.61 mΩ-cm2 under the Vgs-Vth= 5 V and LOCOS spacing d= 6 μm situations.

Keywords: Breakdown voltage; High Voltage (HV); Local Oxidation of Silicon (LOCOS); N-channel lateral-diffused MOSFET (nLDMOS); Onresistance

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