High Reliabilities Design of Stacked Ultra-High-Voltage nLDMOSs in a 0.5-μm BCD Semiconductor Technology

High holding voltage of the stacked circular ultra-high voltage (UHV) nLDMOS component with slightly lowered ESD ability is developed by a TSMC 0.5-μm Bipolar-CMOS-DMOS (BCD) process. The holding voltage is an important parameter concerned with the latch-up immunity in a CMOS IC. In general, the holding-voltage value of a traditional nLDMOS is much lower than the supply voltage (VDD), there has high latch-up risk. In this paper, a stacking architecture of nLDMOS transistors is used to investigate the ESD ability and latch-up immunity. From experimental results, as three nLDMOS DUTs were stacked, this component has a highest holding voltage up to 180.59-V and a relatively vigorous ESD capability under without altering the operating voltage of the DUT.

Keywords: Electrostatic discharge (ESD); Holding voltage (Vh); Latch-up (LU); Lateral-diffused MOSFET (LDMOS); Transmission-line pulse (TLP); Ultra-high voltage (UHV)